LLM-based Code Generation for Verilog
Anshul Raghav, Mark Santolucito
Affiliation: Redmond High School
IJSCAR Vol. 2, Issue 1 (2025) · pp. 23–32
Abstract
Recent advancements in Large Language Models (LLMs) have transformed code generation across various programming languages. However there remains a significant gap in research regarding their application to hardware description languages particularly Verilog. This gap is especially critical as hardware development becomes increasingly complex and automated assistance could substantially reduce development time and minimize errors in system design. To address this challenge we conducted a comprehensive ablation study comparing GPT-4o GPT-4o mini and GPT-3.5 Turbo for Verilog code generation. Our methodology involved evaluating four distinct approaches: (1) one-shot generation as a baseline (2) multi-shot generation (3) an error correction pipeline for handling compilation errors and (4) a full framework that addresses both compilation and functional errors. Our results demonstrate that the full framework significantly outperforms baseline approaches across all tested models. The results show that the full framework outperformed all baseline methods eliminating compilation errors entirely and increasing the overall pass rate by up to 17.65%. In the ablation study the multi-shot generation and error-handling components demonstrated incremental improvements of 1.96% and 5.88% respectively underscoring the contribution of each component to the framework’s effectiveness.
Keywords: Verilog, Code Generation, LLMs, Ablation Study